When two digital logic devices having different power supply levels are coupled together, an interface circuit is generally required to prevent damage to transistors in the device having the lower power supply level. The interface circuit should also minimize leakage current and prevent latch-up.
For a given power supply voltage, the electric field strength, e.g. the change in voltage per unit length, that transistors are exposed to increases as the size of the transistors is reduced. Digital semiconductor devices have typically been powered by 5V supplies. The maximum electric field tolerance can be a limiting factor on the minimum transistor size. For example, a typical maximum gate oxide field strength for silicon dioxide gates is about 3 megavolts per centimeter. High electric fields inside a transistor can reduce the mean time to failure, and can destroy transistors when an electric field exceeds the breakdown value for a given material in a transistor, such as the gate oxide in CMOS devices.
To reduce the minimum transistor size imposed by the electric field, certain types of digital logic devices including CMOS devices are now powered with a 3.3V supply rather than a 5V supply. However, these 3.3V digital logic devices must often be connected to logic devices that operate with 5V supplies, such as, for example, TTL devices. Absent some form of protection, the 5V TTL signals can damage the 3.3V digital logic devices.
Programmable devices typically include pins that can be used for input or output signals depending upon how the device is programmed. These pins are called I/O pins or I/O terminals. An interface structure must be provided between the I/O pin and the internal portions of the programmable device. The interface structure operates in two modes: input pin mode and output pin mode. The interface structure connects to a DATA OUT line for receiving a data-out signal from the internal portions of the device. The interface structure connects to a DATA IN line for sending a data-in signal to the internal portions of the device. When the I/O pin is being used as an output pin, the interface structure buffers the data-out signal and applies it to the I/O pin. When the I/O pin is being used as an input pin, the interface structure places all output buffer drivers into a tristate mode, thus disconnecting them from the I/O pin so that an input signal applied by an external source to the I/O pin does not conflict with a signal on the DATA OUT line. The input signal is then typically buffered and applied to the DATA IN line.
A 3.3V device can safely drive its own I/O pin when the I/O pin is being used for output. However, when the I/O pin of a 3.3V device is being driven by a neighboring 5V device, the 3.3V device must include protection circuits attached to the I/O pin. One prior art approach to protecting 3.3V digital logic circuits is to provide diodes at the power supply of the 3.3V device to limit the maximum voltage at the I/O pin common to the low and high voltage devices. In these devices when an external voltage is applied to an I/O pin that is sufficiently greater than the power supply voltage, the power supply diode turns on and draws current. This approach has a drawback of creating large leakage currents and increasing the power dissipation. Other approaches to providing an interface between digital logic devices with different voltage tolerance levels suffer from a variety of drawbacks. Some require a 5V power supply, others reduce the noise immunity of the circuit and increase the vulnerability of the circuit to latch-up, and still others require costly fabrication processes to produce a plurality of types of transistors of the same polarity with different threshold levels. Thus an improved low voltage I/O circuit with a high voltage tolerance that avoids these and other prior art problems is needed.